module FIFO(sysclk,reset,coderFifoWrite,coderFifoData,uartFifoReq,
            FifoUartEmp,FifoUartFull,FifoUartData,counter);
parameter WIDTH=8;
parameter DEPTH=32;

input sysclk,reset,uartFifoReq,coderFifoWrite;
input [WIDTH-1:0] coderFifoData;
output [WIDTH-1:0] FifoUartData;
output FifoUartEmp,FifoUartFull;
output reg [3:0] counter;
reg [WIDTH-1:0] FifoUartData;
reg [3:0] uartFifoReq_ptr,coderFifoWrite_ptr;

reg [WIDTH-1:0] ram [DEPTH-1:0];

always @(posedge sysclk)
         if(reset)
                 begin
                    uartFifoReq_ptr=0;
                    coderFifoWrite_ptr=0;
                    counter=0;
                    FifoUartData=0;
                end
   else // mod is same with the uartFifoReq ptr,this means we need to stop;
                case({uartFifoReq,coderFifoWrite})
                        2'b00: counter=counter;
                        2'b01: begin
                                 ram[coderFifoWrite_ptr]=coderFifoData;    
                                 counter=counter+1;
											coderFifoWrite_ptr=(coderFifoWrite_ptr==15)?0:coderFifoWrite_ptr+1;
                                 end
                        2'b10: begin
                                 if(FifoUartEmp);
                                 else begin
                                 FifoUartData=ram[uartFifoReq_ptr];
                                 counter=counter-1;
                                 uartFifoReq_ptr=(uartFifoReq_ptr==15)?0:uartFifoReq_ptr+1;
                                 end
                                 end
                        2'b11: begin
                                if(counter==0)
											FifoUartData=coderFifoData;
                                else
                                begin
                                 ram[coderFifoWrite_ptr]=coderFifoData;
                                 FifoUartData=ram[uartFifoReq_ptr];
                                 coderFifoWrite_ptr=(coderFifoWrite_ptr==15)?0:coderFifoWrite_ptr+1;
                                 uartFifoReq_ptr=(uartFifoReq_ptr==15)?0:uartFifoReq_ptr+1;
                                end
                                end
                endcase
assign FifoUartEmp=(counter==0);
assign FifoUartFull=(counter==31);//I have changed from 15 to 16
endmodule
